USB PHY Solution

Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. The USB2.0 OTG PHY supports the USB2.0 480Mbps protocol and data rate, and is backward compatible with the USB 1.1 1.5Mbps and 12Mbps protocol and data rates. It has been verified by a number of end products, especially suitable for the current popular internet of things applications.



  • Supports High-speed, Full-Speed and Low-Speed data rates

  • Supports Host, Peripherals and OTG application

  • Fully Compliant with UTMI + Level 3 Specification

  • Supports internal PLL for High-Speed(480MHz) Clock and Data Recovery operation

  • Support Built in Self-Test(BIST) for production testing

  • Including digital and analog loop back test for HS/FS/LS mode to facilitate testing and debugging

  • Integrated Termination Resistors (50Ω, 1.5K, 15K) with auto calibration to meet high accuracy

  • Support 8-bit 60MHz and 16-bit 30MHz parallel interface

  • Clock and Data Recovery implemented fully by adjustable digital with edge detection to maximizing noise filtering for various applications

  • Area and power consumption advantage over competitors



  • Datasheet

  • User's Manual

  • Package/PCB guideline

  • SDK (standard design kit) including verilog model, .lib/.db file, .lef file