YouMIPI
CSI2 Interface Solution
Brite provides full solution for the MIPI CSI interface, which receives the data from sensors in PHY layer, and then converts the byte data to pixel after lane data mergence. Data scramble is an optional feature to decrease the EMI effect. A standard PPI interface is implemented for the connection between MIPI PHY and CSI controller. Brite MIPI CSI interface solution supports image applications with varying pixel formats.
Brite MIPI CSI Interface Solution
Compliant with MIPI CSI-2 Specification v3.0, v2.1, v2.0, v1.3, v1.1, v1.0
Compliant with D - PHY Specification v2.1, v2.0, v1.2, v1.1
Compliant with C - PHY Specification v1.2, v0.7
Full MIPI CSI-2 RX functionality where either D - PHY / C - PHY can be used
Supports Multi lane distribution and also lanes can be configured up to 3 lanes for C - PHY and 8 lanes for D - PHY
Supports Data rate in range 2.5 Gbps
Supports PPI Interface
Supports short and long packets
Supports multilane distribution
Continuous and non-continuous (gated) D-PHY byte clock support
Supports Frame and Line Synchronization Packets (Short Packets)
Supports Data Descrambling in Lanes
Supports Deskew mechanism for Lane synchronization
Supports High Speed and Escape Mode (LPDT and ULPS) reception
Supports the following interleaving methods
- Data type
- Virtual channel
Supports 16 interleaved Virtual channel in D - PHY and 32 in C - PHY
Support all Protocol Decoding Level errors
Supports the compression for RAW data types
Supports Error Detection techniques for active data using Checksum (16 bit)
Supports Image applications with varying Pixel formats
- RAW Data Type - RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
- RAW16, RAW20, RAW24
- RGB Data Type - RGB444, RGB555, RGB565, RGB888, RGB 666
- YUV Data Type - YUV422-8bit, YUV422- 10bit, YUV420-8bit
- YUV420- 10bit, Legacy YUV420-8bit
- User defined data type - 8 data types
- Generic 8bit long packet (Null, Blanking, Embedded data)
Supports Pixel Level /interface with HSYNC, VSYNC, DATA and DATA VALID
Programmable synchronization and interrupt (error and information) events
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices
PHY Features:
The Brite MIPI DPHY RX integrates 1 clock lane and up to 4 Data lanes, which is compatible with the D-PHY V1.2 specification. The high speed receiver supports 80Mbps up to 2.5Gbps data rate, low-power receiver and transmitter both support data transmission around 10Mbps. As the same as TX, the interface is a standard MIPI D-PHY PPI interface that can be easily connected to a standard CSI controller.
Features:
On-die automatic termination calibration to PVT.
Automatic termination control for HS and LP modes.
MIPI-HS/MIPI-LP modes Support.
BIST
PRBS Checker
DSI2 Interface Solution
Brite provides a complete MIPI DSI2 solution, which is compliant with MIPI DSI-2 specification. It supports 1 to 4 lane configuration and different data formats, which can adapt to diverse application scenarios. The DPHY can support crystal or SOC clock input as reference clock, and the data lane sequence can be freely swapped. The interface between controller and PHY is a standard PPI interface.
Brite MIPI DSI Interface Solution
Controller Features:
Compliant with MIPI DSI-2 Specification v1.3
Compliant with Display Serial Interface (DPI -2) v2.0
Supports fully MIPI DSI2 Transmitter functionality
Compliant with Display Bus Interface (DBI) v2.0
Compliant with Display Command Set (DCS) v1.3
Compliant with D - PHY specification v2.1, v2.0, v1.2, v1.1
Compliant with C – PHY specification v1.2
Full MIPI DSI-2 Receiver functionality supporting CPHY and DPHY
Supports all types of short and long packets
Supports 1 to 4 lane configuration and 3 trios
Supports internal data width of maximum up to 128 bits
Supports PPI interface with 8/16/32 bit
Supports all virtual channel identifier
Supports both video and command modes
Supports Multiple packets per transmission
Supports Error Detection techniques for active data using Check sum (16 bit)
Interrupt support for indicating internal status and error information
Supports sync event payloads and Data Interleaving
Programmable display resolutions
Supports for dual MIPI DSI use case with VESA display stream compression (DSC)
Supports generic read / write over DBI Interface
Supports burst and non-burst mode transfer over DPI Interface
Supports all BTA (Bi directional Turn around) with contention and fault recovery
Supports Bi-directional communication and escape mode
Supports EOT Enable/ Disable Mechanism
Supports Link Merging Function
Supports both High speed and Low power packet reception
Multiple peripheral support capability with configurable virtual channels Supports for ultra- low power mode
Supports following formats
- YCbCr Data type
- RGB Data type
- YUV Data type
- RAW Data type
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices
PHY features:
The Brite MIPI DPHY TX integrates 1 clock lane and up to 4 Data Lanes compatible high-speed receiver that support 80Mbps up to 2.5Gbps Data rate, low-power receiver and transmitter that supports data rate around 10Mbps. This IP supports D-PHY v1.2 specification. The interface is a standard MIPI D-PHY PPI interface that can be easily connected to a standard DSI controller.
As well, the Brite MIPI DPHY TX consists of many key components which provides a variety of functionality:
On-die automatic TX termination calibration.
SCAN and BIST modes.
Flexible input clock reference
Lane Swap supported
Internal reference clock or external crystal oscillator support
