ASIC SERVICE
Efficient ASIC Flow

  Efficient ASIC Methodology Flow


  

Key design techniques

  • Code  purification/Code coverage

  • DFT/Synthesis/Low   power analysis

  • Constraint and CDC   checks

  • DCT-SPG/RCP   physical synthesis for HPC

  • UPF/CPF low power   design

  • Multi-bit register   for low power optimization

  • MBIST design   (shared-bus model) for high speed CPU core (A7/A15 etc.)

  • Low/Full-speed DFT   design with high coverage

  • DFT logic/physical   aware diagnosis flow

  • Experts on   Floor/Power plans, and ESD/Latch up checks

  • Efficient timing   budget design flow

  • Bump assignments   and RDL routing

  • Cadence CCOpt CTS   for high performance design and power optimizations

  • MCMM timing/power   optimizations

  • Low power design   implementations

  • Enable DFM   implementations and automatic fixing

  • MCMM STA/SI timing   signoff

  • Static/Dynamic   IRDrop power signoff

  • EM signoff   (power/signal) and DFM signoff

  • DRC/LVS/ERC signoff

  • PERC signoff for   ESD checks

  • Function pattern   generations and validation

  • DC/AC ATPG normal   & diagnosis pattern generations and validation

  • MBIST normal &   diagnosis pattern generations and validation