Serdes System Engineer
• The candidate will participate development of PCIe related product;
• The candidate will develop PCIE protocol and hardware model;
• The candidate will run test cases, design micro-architecture, and simulation;
• Proficiency in Matlab, Simulink, C/C++, Python;
• Strong knowledge in digital hardware architecture, communications Systems, signal processing, algorithms;
• Strong knowledge of communication protocol. Experience with PCIe (or similar) PCS/MAC protocol is a big plus;
• Working experience on Serdes and modem ASIC development;
• Experience on system modeling, hardware modeling, computer micro-architecture design and modeling;
Senior Digital Design Engineer
1. Provide digital design support to complete mixed signal IP.
2. Perform mixed-signal co-simulations to ensure accurate block level functionality with integrated analog circuits.
3. Logic Synthesis, Static Timing Analysis and Logic Equivalency Checking
4. Design for test, scan insertion, ATPG, Functional Test Vectors
5. Interface with Place and Route Engineering to perform timing check and back-annotated simulations.
6. Ensure database integrity before any release.
7. Execute any project assignment in the timing manner.
8. Follow company’s quality standards during any project execution.
1. At least 3 or more years of RTL level digital design experience with MS in EE or related (more senior levels will also be considered)
2. Willing to work as an active team player with group’s goal in mind.
3. Experience in writing simple digital models or real number models for analog IPs
4. Knowledge with process and device physics is a plus
5. Acceptable communication skill in written and spoken English
Sr. P&R engineer
1. Responsible for the development and support of customer based design form netlist to GDS tape out;
2. Responsible for VLSI chip floor plan;
3. Responsible for CTS, Power plan, Placement & Routing, SPF extraction;
4. Responsible for whole chip DRC/LVS, and GDS tape out.
1. 3+ years of experience and minimum of BS in EE or equivalent; MS is a plus. Experienced in one of the major P&R (Place & Route) tool suites (Cadence, Synopsys, Mentor, or Magma);
2. Background in timing closure and signoff (PrimeTime experience);
3. Scripting expertise (Perl, Tcl, or Python) a strong plus;
4. Actual chip tapeout experience on a recent technology node (65nm or below) a strong plus.
● 应届本科/硕士毕业生
● 微电子、半导体及电子类相关专业
● 专业成绩优异
● 有半导体行业实践经验者优先
● 英语优秀(CET6)
● 善于沟通及团队协作
● 有敬业精神
ASIC DFT Engineer
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SoC design;
2. Generating, simulation and debugging the test patterns for ATE manufacture testing;
3. Interface with back-end physical design team to complete timing closure for test related logic;
4. Interface with operation team to debug production test-vectors for wafer test and final test.
1. BS or MS, major in EE or related discipline;
2. Strong experience in ASIC logic design and verification;
3. 1+ years work experience in ASIC DFT design;
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability;
5. Good communication capability and teamwork spirit.