Marcom Specialist (Shanghai Office)
Job responsibilities
1. Plan & execute Marcom programs and campaigns timely and effectively, including conferences, seminars, exhibitions, trade show and advertising etc.
2. Develop/ manage the production of marketing materials, including leaflets, posters, flyers, newsletters, ad material e-newsletters and DVDs.
3. Support business units on development and execution of advertising and media campaign.
4. Good communication with media, industry association and government.
5. Able to integrate digital marketing seamlessly into all Marcom activities.
6. Manage marketing budgets, vendors & resources effectively to meet target.
7. Collect and analyze marketing information including industry regulations, competitive data, marketing trend, hot products, etc.
Job requirements
1. Bachelor or above in marketing or engineering.
2. Minimum 2 years of related experience in firms of IC design / Semiconductor/ electronics/ high-tech.
3. Proficient PC skills including Word, Excel and PowerPoint, Photoshop.
4. Strong coordination and communication skills
5. Familiarity with Internet and digital communication channels.
6. Fluency in English and Mandarin with outstanding written abilities.
7. Excellent project management skills, attention to details, able to exercise discretion to make appropriate decisions, can cope with pressure, tight timelines and ambiguity.
Product Engineer (Shanghai Office)
Job responsibilities
1. Introduce new customer projects or RND programs from engineering phase to volume production after successful product qualification.
2. PE should coordinate with project manager, internal design teams, customers, foundries and subcontractors for project development smoothly in operation.
3. Be responsible for manufacturing control, failure analysis and issue debugging.
4. Be responsible for product cost-down control, yield analysis and improvement.
5. Bear innovation mind to make continuous improvement.
Job requirements
1. M.S. or B.S. degree in EE or equivalent.
2. Minimum four years of experience in ASIC design or IC manufacturing is required.
3. Have good knowledge of ASIC backend design, IP eco-system, IC manufacturing, testing and packaging and IC market is the basis for this job.
4. Ability to troubleshoot, analyze problems, multi-task and meet deadlines.
5. A qualified program manager has to be able to communicate and educate both internally & externally.
6. Product engineer has to deliver results based on influence rather than authority and excellent interpersonal skills are a must.
7. Proved capability of the presentation and documentation.
8. Fluent in both oral and written English and Mandarin Chinese.
Package Engineer (Shanghai Office)
Job responsibilities
1. Support new projects or RND programs on package type selection, feasibility evaluation for package design and process, preparation of package tooling and bumping masks, and all other issues related to packaging;
2. Be responsible for completing package designs (QFP, QFN, WLCSP& Bumping product or BGA/ FC products) and associated support documentation.
3. Coordinate with customer, design team and subcontractors for package simulation of electrical, thermal and mechanical for variable package types.
4. Be responsible for package qualification and reliability test;
5. Be responsible for transferring engineering product to product engineer in production phase;
6. Manufacturing control, yield analysis and improvement.
Job requirements
1. Good knowledge of IC packaging process (QFP, QFN, BGA/FCBGA, bumping …) is essential;
2. Design of semiconductor substrate or leadframe package products using multiple CAD tools, including Cadence(APD), AutoCAD, CAM350, etc.
3. Good written and oral communication skills in English;
4. Able to manage subcontractors in different locations;
5. Minimum of 2 years of working experience in packaging house or design house; Bachelor degree and above.
Senior Analog Design Engineer (Shanghai/Suzhou)
Job responsibilities
1. Will work on the following analog IPs but not limit to: ADC/DAC, LDO/DCDC, POR, BOR, Band-gap, various amplifiers, PLL/DLL and high speed interface design
2. Be responsible for schematic capture, simulation, test plan, DK generation and bench verification/characterizations.
3. Escort and instruct layout designers to complete physical implementations
4. Ensure database integrity before any release.
5. Execute any project assignment in the timing manner.
6. Follow company’s quality standards during any project execution.
Job requirements
1. At least 3 or more years of analog circuit design experience with MS in EE or Physics (more senior levels will also be considered)
2. Willing to work as an active team player with group’s goal in mind.
3. Familiar with SPICE simulations including Monte-Carlo analysis
4. Strong knowledge in physical layout and component’s parasitic effects.
5. Knowledge with process and device physics is a plus
6. Acceptable communication skill in written and spoken English
7. Experience in Sigma-Delta ADC/DAC is a plus.
Senior PHY Algorithm Engineer (Shanghai/Suzhou)
Job responsibilities
1. Perform physical layer modem algorithm development of BLE, NBIOT or similar wireless standards.
2. Simulate the key modem algorithm of wireless communication with MATLAB.
3. Design the communication protocol of BLE, NBIOT or similar wireless standards.
4. Familiar with DSP or FPGA development tool and technical support to it.
5. Participate the project validation.
Job requirements
1. Master degree or above, two or more year of direct experience.
2. Prefer having experience in modem development of BLE or NBIOT.
3. Master one or two skills of the followings: signal synchronization, detection, estimation, coding/decoding, scrambler/descrambler.
4. Very familiar with MATLAB or C/C++.
5. Can independently perform key algorithm development, understand the high level protocol
6. Good English reading skills.
7. Good attitude and responsibility. Good communication skills and team work.
Senior IP FAE (Shanghai/Suzhou)
Job responsibilities
1. Working with sales, responsible for IP sales.
2. Working with engineering team, responsible for IP support in both pre-sale and post-sale stages.
3. Involved with IP marketing, IP promotion and IP management.
Job requirements
1. B.S. or M.S. in EE or equivalent is required.
2. Proactive and good communication skills.
3. 2 or more years of IP sale or support experience.
4. 2 or more years of analog design experience is preferred.
5. Knowledge of DDR, USB, MIPI, SERDES and fundamental analog IPs, and their applications in SOC and system.
Design & Verification (staff) Engineer (DDR controller/PHY) (Shanghai/Suzhou)
Job responsibilities
1. Maintain and develop current DDR234/LPDDR234 IP.
2. Deep research on current controller/PHY architecture and micro-architecture.
3. Solve the simulation/integration/timing issue from the customer.
4. Add features on current DDR IP and validate
5. Make documents – Diagram/table/description using word and visio.
Job requirements
1. Familiar with AXI/DDR(JEDEC)/DFI specification. B.S. or M.S. in EE or equivalent is required.
2. 3+ years of experience on digital design or verification.
3. Familiar with scripts – Perl and tcl.
4. Familiar with timing concept and SDC.
5. Highly organized and self-motivated.
6. Ability to work with teammates.
7. Good language and communication skills in English for both spoken and written.
Program Manger (Shanghai Office)
Job responsibilities
1. Be in charge of the overall project management, and play the role of main responsible person
2. Work with Sales and account team to establish the relationship with customers
3. Familiar with ASIC design flow and monitor and keep follow up the customer demand and design team progress
4. Understand foundry/package/test operation, and control a project from design to manufactory
Job requirements
1. Bachelor or master degree
2. 3+ experience with project execution in semiconductor industry
3. Be good at logic, research and analysis, can study quickly and solve hard issues
4. Excellent coordination skill and teamwork spirit
PR Engineer (Shanghai/Suzhou/Hefei)
Job responsibilities
1. Responsible for the development and support of customer based design from netlist to GDS tape out, including:
2. ASIC floor plan or complex block (CPU/GPU..) implementation;
3. CTS, Power plan, Placement & Routing, SPF extraction;
4. Whole chip DRC/LVS, and GDS tape out
Job requirements
1. 3-5 years of experience and minimum of BS in EE or equivalent; MS a plus. Experienced in one of the major P&R (Place & Route) tool suites (Cadence, Synopsys).
2. Background in timing closure and signoff (PrimeTime experience).
3. Scripting expertise (Perl, Tcl, or Python) a strong plus.
4. Actual chip tapeout experience on a recent technology node (40nm or below) a strong plus.
DFT Engineer (Shanghai/Suzhou/Hefei)
Job responsibilities
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test
Job requirements
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit